The present invention relates to voltage surge protection devices and, more particularly, to a voltage surge protection device including a wafer of varistor material.
Frequently, excessive voltage is applied across service lines which deliver power to residences and commercial and institutional facilities. Such excess voltage or voltage spikes may result from lightning strikes, for example. The voltage surges are of particular concern in telecommunications distribution centers, hospitals and other facilities where equipment damage caused by voltage surges and resulting down time may be very costly.
Typically, one or more varistors (i.e., voltage dependent resistors) are used to protect a facility from voltage surges. Generally, the varistor is connected directly across an AC input and in parallel with the protected circuit. The varistor has a characteristic clamping voltage such that, responsive to a voltage increase beyond a prescribed voltage, the varistor forms a low resistance shunt path for the overvoltage current that reduces the potential for damage to the sensitive components. Typically, a line fuse may be provided in the protective circuit and this line fuse may be blown or weakened by the essentially short circuit created by the shunt path.
Varistors have been constructed according to several designs for different applications. For heavy-duty applications (e.g., surge current capability in the range of from about 60 to 100 kA) such as protection of telecommunications facilities, block varistors are commonly employed. A block varistor typically includes a disk-shaped varistor element potted in a plastic housing. The varistor disk is formed by pressure casting a metal oxide material, such as zinc oxide, or other suitable material such as silicon carbide. Copper, or other electrically conductive material, is flame sprayed onto the opposed surfaces of the disk. Ring-shaped electrodes are bonded to the coated opposed surfaces and the disk and electrode assembly is enclosed within the plastic housing. Examples of such block varistors include Product No. SIOV-B860K250 available from Siemens Matsushita Components GmbH and Co. KG and Product No. V271BA60 available from Harris Corporation.
Another varistor design includes a high-energy varistor disk housed in a disk diode case. The diode case has opposed electrode plates and the varistor disk is positioned therebetween. One or both of the electrodes include a spring member disposed between the electrode plate and the varistor disk to hold the varistor disk in place. The spring member or members provide only a relatively small area of contact with the varistor disk.
The varistor constructions described above often perform inadequately in service. Often, the varistors overheat and catch fire. Overheating may cause the electrodes to separate from the varistor disk, causing arcing and further fire hazard. There may be a tendency for pinholing of the varistor disk to occur, in turn causing the varistor to perform outside of its specified range. During high current impulses, varistor disks of the prior art may crack due to piezoelectric effect, thereby degrading performance. Failure of such varistors has led to new governmental regulations for minimum performance specifications. Manufacturers of varistors have found these new regulations difficult to meet.
In various embodiments, the present invention is directed to an overvoltage protection device which may provide a number of advantages for safely, durably and consistently handling extreme and repeated overvoltage conditions. The overvoltage protection device may include a wafer of varistor material and a pair of electrode members, one of which is preferably a housing, having substantially planar contact surfaces for engaging substantially planar surfaces of the wafer.
Preferably, the electrodes have relatively large thermal masses as compared to the thermal mass of the varistor wafer so as to absorb a significant amount of heat from the varistor wafer. In this manner, the device may reduce heat-induced destruction or degradation of the varistor wafer as well as any tendency for the varistor wafer to produce sparks or flame. The relatively large thermal masses of the electrodes and the substantial contact areas between the electrodes and the varistor wafer may also provide a more uniform temperature distribution in the varistor wafer, thereby potentially reducing hot spots and resultant localized depletion of the varistor material.
Preferably, the electrodes are mechanically loaded against the varistor wafer. Biasing means may be used to provide and maintain the load. The loading preferably provides a more even current distribution through the varistor wafer. As a result, the device may respond to overvoltage conditions more efficiently and predictably, and high current spots which may cause pinholing are more likely to be avoided. Also, the tendency for the varistor wafer to warp responsive to high current impulses may be prevented or reduced by the mechanical reinforcement provided by the electrodes. Moreover, during an overvoltage event, the device would be expected to provide lower inductance and lower resistance because of the more uniform and efficient current distribution through the varistor wafer.
Preferably, the device includes a metal housing and further components configured to prevent or minimize the expulsion of flame, sparks and/or varistor material upon overvoltage failure of the varistor wafer. The wafer may be formed by slicing the wafer from a rod of the varistor material.
In further embodiments of the present invention, an overvoltage protection device includes a housing including a first substantially planar electrical contact surface and an electrically conductive sidewall. The housing defines a cavity therein and has an opening in communication with the cavity. An electrode member of the device may include a second substantially planar electrical contact surface facing the first electrical contact surface and disposed within the cavity. A portion of the electrode member may extend out of the cavity and through the opening. A wafer formed of varistor material and having first and second opposed, substantially planar wafer surfaces is positioned within the cavity and between the first and second electrical contact surfaces with the first and second wafer surfaces engaging the first and second electrical contact surfaces, respectively.
According to further embodiments of the present invention, an overvoltage protection device for use with a varistor wafer of the type having first and second opposed, substantially planar wafer surfaces includes a housing including a first substantially planar electrical contact surface and an electrically conductive sidewall. The housing defines a cavity therein and has an opening in communication with the cavity. An electrode member of the device may include a second substantially planar electrical contact surface facing the first contact surface and disposed within the cavity. A portion of the electrode may extend out of the cavity and through the opening. The housing and the electrode member may be relatively arranged and configured to receive the wafer within the cavity such that the wafer is positioned between the first and second electrical contact surfaces with the first and second electrical contact surfaces engaging the first and second wafer surfaces, respectively.
In other embodiments of the present invention, an overvoltage protection device for use with a varistor wafer of the type having first and second opposed, substantially planar wafer surfaces includes a housing defining a cavity therein and having an opening in communication with the cavity. The housing includes a sidewall and a bottom wall including a first substantially planar electrical contact surface and an adjacent recessed surface. The first electrical contact surface defines a raised platform relative to the recessed surface. An electrode member of the device may include a second substantially planar electrical contact surface facing the first contact surface and disposed within the cavity. A portion of the electrode may extend out of the cavity and through the opening. The housing and the electrode member may be relatively arranged and configured to receive the wafer within the cavity such that the wafer is positioned between the first and second electrical contact surfaces with the first and second electrical contact surfaces engaging the first and second wafer surfaces, respectively, and such that the wafer does not engage the recessed surface.
According to further embodiments of the present invention, an overvoltage protection device for use with a varistor wafer of the type having first and second opposed, substantially planar wafer surfaces includes a housing including a first substantially planar electrical contact surface and a sidewall. The housing defines a cavity therein and has an opening in communication with the cavity. An electrode member of the device may include a second substantially planar electrical contact surface facing the first contact surface and disposed within the cavity and a shaft extending out of the cavity and through the opening. The shaft may include a circumferential shaft groove formed therein. A closure member may be interposed between the second electrical contact surface and the opening. The closure member may have a hole defined therein. A resilient O-ring may be disposed in the shaft groove. The shaft may extend through the aperture, the O-ring may be disposed in the hole and the O-ring may be positioned to provide a seal between the shaft and the closure member. The housing and the electrode member may be relatively arranged and configured to receive the wafer within the cavity such that the wafer is positioned between the first and second electrical contact surfaces with the first and second electrical contact surfaces engaging the first and second wafer surfaces, respectively.
According to further embodiments of the present invention, an overvoltage protection device for use with a varistor wafer of the type having first and second opposed, substantially planar wafer surfaces includes a housing including a first substantially planar electrical contact surface and a sidewall. The housing defines a cavity therein and has an opening in communication with the cavity. An electrode member of the device may include a second substantially planar electrical contact surface facing the first contact surface and disposed within the cavity. A portion of the electrode may extend out of the cavity and through the opening. A closure member may be interposed between the second electrical contact surface and the opening. The closure member may have a peripheral groove formed therein. A resilient O-ring may be disposed in the peripheral groove. The O-ring may be positioned to provide a seal between the closure member and the sidewall of the housing. The housing and the electrode member may be relatively arranged and configured to receive the wafer within the cavity such that the wafer is positioned between the first and second electrical contact surfaces with the first and second electrical contact surfaces engaging the first and second wafer surfaces, respectively.
According to other embodiments of the invention, an overvoltage protection device for use with a varistor wafer of the type having first and second opposed, substantially planar wafer surfaces includes a housing including a first substantially planar electrical contact surface and a sidewall. The housing defines a cavity therein and has an opening in communication with the cavity. An electrode member of the device may include a second substantially planar electrical contact surface facing the first contact surface and disposed within the cavity. A portion of the electrode may extend out of the cavity and through the opening. An end cap may be positioned in the opening. A clip may be positioned to limit displacement between the end cap and the housing. The housing and the electrode member may be relatively arranged and configured to receive the wafer within the cavity such that the wafer is positioned between the first and second electrical contact surfaces with the first and second electrical contact surfaces engaging the first and second wafer surfaces, respectively.
According to further embodiments of the present invention, a method of installing a truncated ring-shaped clip in a housing, the clip having a pair of opposed end portions each having an aperture formed therein, includes compressing the clip using the apertures. The clip is positioned relative to the housing. The clip is released to allow the clip to engage the housing. Thereafter, the end portions of the clip may be cut.
According to further embodiments of the present invention, a method of installing a truncated ring-shaped clip in a housing, the clip having a pair of opposed end portions each having an aperture formed therein, includes compressing the clip using the apertures. The clip is positioned relative to the housing. The clip is released to allow the clip to engage the housing. Thereafter, a filler material may be placed into each of the apertures.
According to other embodiments of the present invention, an overvoltage protection device for use with a varistor wafer of the type having first and second opposed, substantially planar wafer surfaces includes a housing including a first substantially planar electrical contact surface and a sidewall. The housing defines a cavity therein and has an opening in communication with the cavity. An electrode member of the device may include a second substantially planar electrical contact surface facing the first contact surface and disposed within the cavity. A portion of the electrode may extend out of the cavity and through the opening. First and second Belleville washers may bias at least one of the first and second contact surfaces toward the other. Each of the washers may be tapered along an axis thereof. The first and second Belleville washers are preferably axially aligned and oppositely oriented. The housing and the electrode member may be relatively arranged and configured to receive the wafer within the cavity such that the wafer is positioned between the first and second electrical contact surfaces with the first and second electrical contact surfaces engaging the first and second wafer surfaces, respectively.
Objects of the present invention will be appreciated by those of ordinary skill in the art from a reading of the Figures and the detailed description of the preferred embodiments which follow, such description being merely illustrative of the present invention.